In principle that is correct. Are your Vout+ and Vout- already (cmos, for example) logic levels? If they are, then you do not need to use both but you could just use Vout+ into your encoder. If they are not (cmos) logic levels, you should definitely do Vout+ - Vout- in order to increase immunity to noise and then amplify the difference to a logic level that you can use in your encoder.tiportoolmo said:In order to drive the encoder it's correct to do this operation: (Vout+ - Vout-), where Vout+ and Vout- are the outputs of the second stage comparator?
you do not have to. It was just a suggestion/comment since typically high speed adc are designed using cml or equivalent. A modern process can easily work at 1GHz with full-swing cmos. So, it is up to your process (and you can simulate that!)tiportoolmo said:do you mean I have to use cml logic for the encoder because it's more suitable at high speed and also because the input is differential?
Well, both Vop_c10 and Von_c10 are between 0 and 1.8V(?), when you subtract them you get one signal (Vop_c10-Von_c10) between -1.8 and +1.8 that looks exactly like yours...tiportoolmo said:Really the simulations show the difference between Vop_c10 and Von_c10. I mean, (vop_c10 - von_c10) and not the single value of vop_c10 and von_c10 which are not represented.
Yeah, isn't this what I suggested? You do not need the two inverters (since the output is already at logic level!) unless the load of the dff is too much for the comparator.tiportoolmo said:Maybe I found a solution: the single output vop_c10 drives two stage of inverters to obtain full logic levels and the ouptut of the inverters drives a D-flip flop positive edge triggered.
what do you think? it could be a good solution?
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