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Flash ADC - Which are the inputs of the ENCODER

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tiportoolmo

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I'm designing a full Flash ADC , my project is similar to that one presented in "adc 4 bit.pdf".

I have simulated all the stages and I obtained the same results..Now the problem is: Which are the inputs of the ENCODER?
I mean,if you look to the pdf file,in the first page,section II.System Architecture,at the end of the paragraph the autors write : "Finally the fifteen differential
output are applied to digital decoder circuit."
The differential outputs came from the second stage comparators,so I think I have to do this operation: (Vout+ - Vout-). It is correct?
How can I do that?

Thank you
 

Question about Flash ADC

At GHz speed, they are most likely using some kind of differential logic (CML, for instance).
 

Re: Question about Flash ADC

sorry I didn't understand..can you explain me in more details?

In order to drive the encoder it's correct to do this operation: (Vout+ - Vout-), where Vout+ and Vout- are the outputs of the second stage comparator?

Reading the pdf file seems that it's the right way but I'm not sure and I don't know how to do that.
 

Re: Question about Flash ADC

do you mean I have to use cml logic for the encoder because it's more suitable at high speed and also because the input is differential?
 

Re: Question about Flash ADC

tiportoolmo said:
In order to drive the encoder it's correct to do this operation: (Vout+ - Vout-), where Vout+ and Vout- are the outputs of the second stage comparator?
In principle that is correct. Are your Vout+ and Vout- already (cmos, for example) logic levels? If they are, then you do not need to use both but you could just use Vout+ into your encoder. If they are not (cmos) logic levels, you should definitely do Vout+ - Vout- in order to increase immunity to noise and then amplify the difference to a logic level that you can use in your encoder.

Added after 3 minutes:

tiportoolmo said:
do you mean I have to use cml logic for the encoder because it's more suitable at high speed and also because the input is differential?
you do not have to. It was just a suggestion/comment since typically high speed adc are designed using cml or equivalent. A modern process can easily work at 1GHz with full-swing cmos. So, it is up to your process (and you can simulate that!)
 

Re: Question about Flash ADC

Thanks for help.

To be more detailed I show you this file. It's a power point presentation of the previous pdf file. At the end there are the outputs of the preamplifier,first comparator and second comparator. I have obtained the same results and as you can see the differential output of the second stage comparator ( Vout+ - Vout-) has logic levels VDD and -VDD, but Vout+ and Vout- have not logic levels.

So I think I have to do (Vout+ - Vout-) to drive the encoder.
What do you think?
 

Question about Flash ADC

The vop_c10 and von_c10 look like logic levels to me (1.8V logic?). When the clock is high, the comparator is in reset mode, hence the zero output; when the clock is low, the comparator makes a decision. You can use vop_c10 as input to your logic (after capturing that on the rising edge of the clock to extend the output of the comparator to a full clock cycle).
 

Re: Question about Flash ADC

Really the simulations show the difference between Vop_c10 and Von_c10. I mean, (vop_c10 - von_c10) and not the single value of vop_c10 and von_c10 which are not represented.
Maybe I found a solution: the single output vop_c10 drives two stage of inverters to obtain full logic levels and the ouptut of the inverters drives a D-flip flop positive edge triggered.

what do you think? it could be a good solution?
 

Re: Question about Flash ADC

tiportoolmo said:
Really the simulations show the difference between Vop_c10 and Von_c10. I mean, (vop_c10 - von_c10) and not the single value of vop_c10 and von_c10 which are not represented.
Well, both Vop_c10 and Von_c10 are between 0 and 1.8V(?), when you subtract them you get one signal (Vop_c10-Von_c10) between -1.8 and +1.8 that looks exactly like yours...
tiportoolmo said:
Maybe I found a solution: the single output vop_c10 drives two stage of inverters to obtain full logic levels and the ouptut of the inverters drives a D-flip flop positive edge triggered.

what do you think? it could be a good solution?
Yeah, isn't this what I suggested? You do not need the two inverters (since the output is already at logic level!) unless the load of the dff is too much for the comparator.
 
Re: Question about Flash ADC

Thanks Joannes for your replies.

Now I show you my simulations:

InPreamplifier shows the differential oputput of the T/H circuit and Vref+ - Vref-

OutComp2Differential shows the output of the second stage comparator. It's the same of (vop_c10 -von_c10)

FinalOutputs shows the outputs of the T/H,second stage compatrator and the orange line shows the outputs of the D-flip flop.

I think it's correct beacuse I have this kind of outputs: 1110 1110 1110 ........Infact as you can see in the figure "InPreamplifier", Vin>Vref three times during the input period (The comparison happen during the negative half of the clock) and one times is Vin< Vref, so I expected to have this kind of outputs : 1110 1110 1110....

Do you think it's correct?
 

Question about Flash ADC

The waveforms look OK to me (I guess you are using ideal T/H). If you really want to see if this is correct, do an FFT of your ADC output and check the SNDR.
 

Re: Question about Flash ADC

Thanks for all your replies!

In order to check the SNDR I have to put an ideal DAC at the output of the ADC, isnt'it?
 

Question about Flash ADC

No, you just need to add the adc output bits with their proper weight in the calculator (and maybe divide the sum by the supply voltage). It is like using an ideal dac but it will save the simulation time.
 

Re: Question about Flash ADC

Please can you explain me using an example?

thanks
 

Question about Flash ADC

let's say you have a 3-bit adc, in the calculator:
(VT("/bit<0>")+2*VT("/bit<1>")+4*VT("/bit<2>"))/3.3

where 3.3 is your supply voltage (so that the reconstructed waveform is between 0 and 7).
 

Re: Question about Flash ADC - help needed

I have a littel problem,i want to do the same analysis as in the attachment..but to da that I need a 5-bit ideal DAC.

Someone has a verilog-A code of a 5 bit ideal DAC?
 

Re: Question about Flash ADC - help needed

hi...
we are doing a project on measuring a analog voltage from the circuits junction
and converting it into digital using adc0804 and the converted data is displayed on lcd,
our problem is we are getting junk values and even correct values for certain voltage ,if the vltge is below2.5 the adc is getting heated up.


:cry::cry:so plz help us we are runnig with shortage of time:cry::cry:
 

Re: Question about Flash ADC - help needed

can you pls tell me what are u using as an encoder

the comparator outputs are to be fed to the encoder, but i have used xor circuit as the encoder
is it right or wrong
pls help
 

Re: Question about Flash ADC - help needed

Try this
for a 3 bit flash adc use 8 resistors(the 1st and the last resistors should be half of the resistance of the rest resistors)
then connect 7 comparators with the reference input through the resistors
the 7comparators outputs should then be feed to thermometer output(xor gates)
the xor outputs should then be feed to encoder inputs
the encoder outputs are the ultimate result for the 3bit flash adc
 

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