koppolu1981
Junior Member level 3
Hi All,
I have done Asic-synthesis of mys using DC and STA using PT. I have specified all paths between clock-domians as fasle paths.
For my Gatelevel simulation with SDF back-annotation I'm seeing violations on signals crossing the clock domains.
If I get the complete false_path for my design, I can disable all the clock crossing violations in GLS.
Can anybody tell me how to get the report of all false paths in either DC/PT?
Thanks in Advance,
Ram
I have done Asic-synthesis of mys using DC and STA using PT. I have specified all paths between clock-domians as fasle paths.
For my Gatelevel simulation with SDF back-annotation I'm seeing violations on signals crossing the clock domains.
If I get the complete false_path for my design, I can disable all the clock crossing violations in GLS.
Can anybody tell me how to get the report of all false paths in either DC/PT?
Thanks in Advance,
Ram