you're right, you could try to over constraint the synthesizer. The best way is to find the trade off area/timing constraint to have the best timing with a reasonable area. Same trade-off during the hold time, increase the margin till the number of buffer added for the hold time is reasonable.
Depending when the setup violation appears, the solution is differents. At synthesis step, you may need to change the RTL or the constraints, after placement with optimisation, depending the gravity of the violation, synthesis could be require or force the tool to fix, same after CTS/hold/routing phases.
Yes if the placement phase does not report any violation, that's mean the synthesis is "good", be sure the PR understood the sdc correctly, and does not "ignore" some timing constraints or extended other ones.