fixing setup violations...

[ee1]

Hi,
i have finish routing my design and having ~25 setup violations.... (0.04 - 0.4 ns)
I have read and understand the causes for setup violations, but having trouble fixing them..

Where should i start?
anyone have some prctical tips?

in addition i am getting 1 "multiport net" violation, what is the causes for this?


I am new in the asic desing area and you guys and the forum are beeing very helpfull!
Thanks!

 

[rca]

1- when you indicate there is some remaining violations, are there reported by the PR tool or STA tool?
2- both tools reported the same violations?
3- if the PR tool reported also the violations, did you made some optimisation post routing?
4- I hope, your report is done with SI enable, if you are below 0.18um?
5- for the multiport net violation, you need to check it, if it is a true or "false"

 

[qual_ti]

Hi,

search for common paths first.
then try to upsize that common cells in that max path.it reduces setup violations...

 

[ee1]

rca -
yes i am getting simmilar resualts in both tools, and made post routing optimization.

5 - what is "it"?.. what exectly shuld i check?...

what actions would you suggest to continue ?...

---------- Post added at 15:59 ---------- Previous post was at 15:54 ----------

qual_ti - this solutions is usuefull in any time violation? or mosly in small ones?
and another question - this can cause a new hold violation right?

 

[qual_ti]

yes. it may come.

what is the actual problem of fixing that timing vioaltion ?

 

[ee1]

that this is my first time fixing setup violation
so i dont really know where to start...
(for example in transition fixing it was easier, i used size cell or add buffer depending on the path..)
and with these violation i am alittle confused...

 

[rca]

Hi ee1,

5- check the netlist to understand the multiport net violation

a- At which step of the backend flow, the setup violation were reported the first time. It is during the routing phase, you could increase the margin for the placement step. If the violation was already present after the placement optimisation, you should look at the synthesis, and so. It is very difficult for the tool to improve later in the flow. It is better to add "enough" margin during the synthesis and after reduce the constraint along the flow, and to use the realistic+margin constraint during the STA.

 

[ee1]

ok!
thanks for the practical tips.
i will try to go and check the design for violations in the previous steps in my flow..
by "add enough margin during synthesis" you mean that i can define severe constraints during synthesis so that afterwards i will be able to meet timing with my original constraints?

another question -
fixing manually setup violation is an option? what option do i have execpt speeding up the path?

thanks!

---------- Post added at 17:40 ---------- Previous post was at 17:32 ----------

a quick check shows that the violation doesnt exist after placement.
they occure right after i route the design...
it means the synthesis is ok, right?

 

[rca]

you're right, you could try to over constraint the synthesizer. The best way is to find the trade off area/timing constraint to have the best timing with a reasonable area. Same trade-off during the hold time, increase the margin till the number of buffer added for the hold time is reasonable.

Depending when the setup violation appears, the solution is differents. At synthesis step, you may need to change the RTL or the constraints, after placement with optimisation, depending the gravity of the violation, synthesis could be require or force the tool to fix, same after CTS/hold/routing phases.

Yes if the placement phase does not report any violation, that's mean the synthesis is "good", be sure the PR understood the sdc correctly, and does not "ignore" some timing constraints or extended other ones.

 

[ee1]

can you explain what you mean by:
" The best way is to find the trade off area/timing constraint to have the best timing with a reasonable area."
thanks!

 

[rca]

I mean, some data path structure could support hight frequency with very few area increase. Then you have a highest frequency, so more margin for less area impact. But, there are some threshold, where the area will increase more than the frequency will increase.

is it more clear?

 

[ee1]

yes, thanks!

 

[ee1]

Hi,
can i fix the setup violation by fixing clocks skew? and how can i do it?
and does fixing crosstalks can help in fixing setup violations? (because it helps with transition violations, right?)
thanks!

 

[rca]

I nor really sure that the skew could help for the setup.
During the placement, the setup is fix with a clock perfect. The clock tree try to have all the flop seen the edge at the same time, then the data path is not directly modified (only data logic could be moved to help the clock tree).
So ....

---------- Post added at 07:39 ---------- Previous post was at 07:38 ----------

In the same idea, the transition violation is not fix by the clock tree, no?