nikhilindia85
Member level 4
hi guyz.i have designed a 32 bit MIPS processor.i have synthesized my design in cadence RTL compiler.i have defined clock period as 15000picosec in synthesis.i got critical delay of 9000ps and slack 6000ps.so from critical delay my max freq is atleast 100Mhz.but my design is not working at 100mhz.some output signal are not able to produce the ouputs at 100mhz.design is working only at 10mhz.why it is happening and how can we improve clk freq