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fixing frequency in post synthesis simulation

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nikhilindia85

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hi guyz.i have designed a 32 bit MIPS processor.i have synthesized my design in cadence RTL compiler.i have defined clock period as 15000picosec in synthesis.i got critical delay of 9000ps and slack 6000ps.so from critical delay my max freq is atleast 100Mhz.but my design is not working at 100mhz.some output signal are not able to produce the ouputs at 100mhz.design is working only at 10mhz.why it is happening and how can we improve clk freq
 

sumit_techkgp

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There is no way u can improve. Please check whether the constraints are applied properly or not. Still if u get such problems, I think u need to pipeline the datapath. Also check wheter the ports are registered or not, this is very important as u are trying to synthesize in a little higher speed!
 

nikhilindia85

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how to pipeline tha critical path.actually i know the concept of piupeline,but i dont know how to apply it.plz anyone can elaborate on it.
 

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