I've seen some examples on how to fix it if your using DC.. I don't have DC however, so is there a way i can manually edit the verilog to remove the assign (I only have 4 of em).. or atleast a way to solve the problem either in Silicon Ensemble or Build Gates..
i did try setting OUTPUT.VERILOG.NO.ASSIGN to TRUE in SE, but it still puts assigns anyways..
hi u have to 2 ways to replace assign in netlist. one is way enable avoid assign statement in netlist by putting buffer insert of it.
otherwise write a script replace all assign statement and put buffer on it.
if u manually add buffer to netlist carefully .
then load that netlist on see any hanging nets are avaible after u did.
if not then u can give the netlist to SE/SOC encounter
it will fix all other routing issues.
i think it give any more problem in LVS
if u need more help
if u manually add buffer to netlist carefully .
then load that netlist on see any hanging nets are avaible after u did.
if not then u can give the netlist to SE/SOC encounter
it will fix all other routing issues.
i think it give any more problem in LVS
if u need more help