Fixing assign from Silicon Ensemble to IC5141?

[jelydonut]

cdnsusers

I've seen some examples on how to fix it if your using DC.. I don't have DC however, so is there a way i can manually edit the verilog to remove the assign (I only have 4 of em).. or atleast a way to solve the problem either in Silicon Ensemble or Build Gates..

i did try setting OUTPUT.VERILOG.NO.ASSIGN to TRUE in SE, but it still puts assigns anyways..

thanks

jelydonut

 

[aravind]

hi u have to 2 ways to replace assign in netlist. one is way enable avoid assign statement in netlist by putting buffer insert of it.
otherwise write a script replace all assign statement and put buffer on it.

 

[jelydonut]

If I manually add a buffer to the netlist i'll hafta manually layout the buffer and connect it up just to pass LVS..

There has to be a easier way..

jelydonut

 

[aravind]

if u manually add buffer to netlist carefully .
then load that netlist on see any hanging nets are avaible after u did.
if not then u can give the netlist to SE/SOC encounter
it will fix all other routing issues.
i think it give any more problem in LVS
if u need more help

try www.cdnsusers.org
forum

 

[Atre]

if u manually add buffer to netlist carefully .
then load that netlist on see any hanging nets are avaible after u did.
if not then u can give the netlist to SE/SOC encounter
it will fix all other routing issues.
i think it give any more problem in LVS
if u need more help

try www.cdnsusers.org
forum

Hello there,
the link you wrote (the one with the forum) does not exist?? I could not connect because it wasn't found.

Thanks!

 

[aravind]

http://cdnusers.org/

try this .
ask same question on it.
there u cadence employee will reply u

have a nice day

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