fixed point to floating point conversion in Verilog

[marufsust]

HI,
I am Masters Student. for my project purpose i need some floating point calculation. but the input is in 16bit fixed point value. I need to convert this 16bit fixed value to IEEE64 bit Floating format.

7380H = 0111 0011 1000 0000
convert into
0 (100 0000 1101) (1100 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000)

can anyone help me how could i do it in VERILOG?

thanx in advance
MAruf

 

[FvM]

The operation involves:
- conversion of 2's complement to sign-magnitude representation (for negative numbers)
- normalization (shift left until MSB = 1, adjust the exponent respectively)

 

[marufsust]

I tried my code is like this

module normalize_integer(clock,operand,result);
input clock;
input [15:0] operand;
output [63:0] result;

reg [4:0] i = 5'b01111;
reg [15:0] store;
reg [51:0] mantissa;
reg [10:0] exponent;

reg [63:0] result;

always@(posedge clock)
begin
store <= i?(operand==1'b1)?i:i<=i-1'b1:0;
exponent <= 11'b01111111111 + store;
mantissa <= operand <<< (52-store) | 52'b0;
result <= {1'b0,exponent,mantissa};
end
endmodule

but its not working

 

[FvM]

The code would be a good candidate for a newspaper's quiz page.
There's no harm in placing only one assignment per code line and using the redundant space for a comment.

At least the exponent calculation seems wrong. The code only handles unsigned numbers. But generally, I would expect something like this.

The combination of a clocked iteration for store and an n-fold shift of the mantissa is most likely not optimal for hardware implementation. You would either try to calculate the result in one cycle, or shift the mantissa incrementally.

 

[marufsust]

Ya you are right. Its wrong code. But i am new to verilog. do you please clarify a bit more? Or ny suggestion how to fix this issue?