Fix point Arithmetic

Status
Not open for further replies.
S

sheikh

Advanced Member level 4
Joined
Sep 10, 2007
Messages
104
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
2,008
Hello Dear
I want to use some arithmetic operations such as (+,_,*) in my design. The design is fix point. Could you please tell me, If I use (+,_,*) symbols in my vhdl code, is it synthesize correctly or not? Or I need to design the units ( n_bit full adder, for instance) then write the code structurally. ( consider it that, I don't start to coding, because I'm not sure about the true way)
Regards
Mostafa
 

+ - * are synthesizable - the performance between one device to another will vary because of the actual implementation of the synthesis tool , different architecture and available "hardened" logic components on the silicon die...

Division however, is synthesizable for constants and 2^n numbers only...you'll have to built your own logic if you want to do division
 
Last edited:
Reactions: sheikh

    S

    sheikh

    Points: 2
    Helpful Answer Positive Rating
Thanks Dear shaiko
Could you please tell me which one is better for a design?
1_ using structural coding. 2_ using symbols ( I mean, using "+", instead of an adder unit)
Thanks in advance
Mostafa
 

Unless you're required to use specific logic components that may be inaccessible with the regular arithmetical operators - I see no point to use structural coding.

- - - Updated - - -

Even more, VHDL gives you a great tool (functions) to implement any pure combinatorial logic without resulting to structural coding.
 

Thanks a lot
 

no need to write your own divider. both altera and xilinx provide divider ip cores.

also have a look at the new fixed point vhdl packages. for 93 compatible versions see WWW.vhdl.org/fphdl
 

TrickyDicky,
using IP's means that the user will have to result to structural coding...
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…