FIR Filterfloating point co-efficients not synthesizable

[Sithija Hewavitharana]

Hi all, i have designed a low pass FIR filter in verilog in which co-efficients are in 0.0XXX range.. i tried $realtobits (is it synthesizable?) and i get the following warning..

"System function call realtobits not supported"

how do i implement synthesizable floating point values in my verilog code..please explain with an example..

below is my sample code...




parameter b0 = 8'd7;

b0 is a co-efficient of the FIR filter, and i want b0 to be a value like 0.0015990642151178748

please help...

 

[axcdd]

multiply coefficients by 2^N, round them to nearest integer, then divide the FIR output by N.

 

[jason_bill]

if that coefficient is an input of the filter module, i think you just need to convert that to single precision(32 bit) or double precision(64 bit) and then apply it to the input of the coefficient. you can convert the floating point value to the single precision floating point using this site:
https://www.h-schmidt.net/FloatConverter/IEEE754.html

 

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if that coefficient is an input of the filter module, i think you just need to convert that to single precision(32 bit) or double precision(64 bit) and then apply it to the input of the coefficient. you can convert the floating point value to the single precision floating point using this site:
https://www.h-schmidt.net/FloatConverter/IEEE754.html

I'm not sure you understand what you are suggesting...IEEE754 is a floating point number format, which isn't going to help the OP unless they have IEEE754 compliant multipliers and adders, which will require a lot more resources than a fixed point (or integer) design will require.

 

[jason_bill]

I'm not sure you understand what you are suggesting...IEEE754 is a floating point number format, which isn't going to help the OP unless they have IEEE754 compliant multipliers and adders, which will require a lot more resources than a fixed point (or integer) design will require.

the above question is about floating point and so think the module must be compatible with ieee745 floating point number format.

 

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Reread the OP's first post, the OP doesn't understand trying to build a FIR filter with floating point isn't the best way to approach this in hardware. The OP is obviously coming from a software centric view of design and is just starting to learn about hardware design.

I'm confident the OP doesn't want to build floating point hardware as they were trying to convert the coefficients that are <1 to bits using $realtobits (which isn't synthesizable).

Scaling the values as axcdd suggestd is the correct way to do this.