#### roiberts

##### Newbie

Im designing a FIR filter, in this case a low pass. I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point.

Now, I want to implement this FIR in my FPGA ,with buil in 18x18 multiplier.

So,I transform the coefficient in integer value of max 17 bit (1 bit for sign) ,multipling the bigger coefficient such that arrive < than 2^17 , and cutting the decimal.

That means, all coefficient preserve the precision more than possible when multiplied for a big number.

First question are:

1)I read this operation introduce a DC offset.Why ?

2)Why DC offset is a so big disturbing problem

Please check if next considerations are correct:

Image the input signal comes from a AD of 16 bit for example..When arrive the input signal, every multiplication sure will produce in the worst case 16+18=34 bit.

Last adder must be the more problematic, because (in worst case) will trasport the 34bit info multiplied for N coefficient .

Exsample...If I have 100 Coefficients,the last adders must work with value like (2^34) *100 -->need 8 bit more .

If I have not this bit, input signal must be scaled

So,question 3) is correct the worst case consideraton?

IN base to what I limit my signal input (some test ????)

Thanks very much and excuse for long message

Roberto