goodpranoy
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In the following code if we donot give input before s2 then the state s2 continues indefinitely.
this occurs in the second process(state machine process)
can anyone please suggest a method so that after s2 is reached and when input changes then the state also changes.
this occurs in the second process(state machine process)
can anyone please suggest a method so that after s2 is reached and when input changes then the state also changes.
Code:
library ieee;
use ieee.std_logic_1164.all;
entity mealy is
port (clk : in std_logic;
reset : in std_logic;
enter : in std_logic;
input:in std_logic_vector(2 downto 0);
pc_enable: out std_logic;
alu_enable: out std_logic;
rom_enable: out std_logic;
reg_enable: out std_logic;
ir_enable: out std_logic;
load_a:out std_logic_vector(2 downto 0);
load_b:out std_logic_vector(2 downto 0);
sel: out std_logic
);
end mealy;
architecture behavioral of mealy is
type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,rab,wa,wab,wb,ra); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset='1') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,enter)
begin
case current_s is
when s0 => --when current state is "s0"
next_s <= s1;
when s1 => --when current state is "s1"
next_s <= s2;
when s2 => --when current state is "s2"
if(input ="000") then
next_s <= rab;
elsif(input ="001") then
next_s <= rab;
elsif(input ="010") then
next_s <= rab;
elsif(input ="011") then
next_s <= rab;
elsif(input ="100") then
next_s <= rab;
elsif(input ="101") then
next_s <= ra;
elsif(input ="110") then
next_s <= s9;
elsif(input ="111") then
next_s <= s10;
else
next_s<=s2;
end if;
when s3 => --when current state is "s3"
next_s <= wa;
when s4 => --when current state is "s4"
next_s <= wa;
when s5 => --when current state is "s5"
next_s <= wab;
when s6 => --when current state is "s6"
next_s <= wa;
when s7 => --when current state is "s7"
next_s <= wa;
when s8 => --when current state is "s8"
next_s <= wb;
when s9 => --when current state is "s9"
if(enter='1') then
next_s <= s0;
else
next_s <= s9;
end if;
when s10 => --when current state is "s10"
next_s <= s0;
when rab => --when current state is "rab"
if(input ="000") then
next_s <= s3;
elsif(input ="001") then
next_s <= s4;
elsif(input ="010") then
next_s <= s5;
elsif(input ="011") then
next_s <= s6;
elsif(input ="100") then
next_s <= s7;
end if;
when wa => --when current state is "wa"
next_s <= s0;
when wab => --when current state is "wab"
next_s <= s0;
when wb => --when current state is "wb"
next_s <= s0;
when ra => --when current state is "wb"
next_s <= s8;
end case;
end process;
output_logic:process(current_s)
begin
case current_s is
when s0=>
pc_enable<='1';
alu_enable<='0';
rom_enable<='1';
reg_enable<='0';
ir_enable<='0';
load_a<="UUU";
load_b<="UUU";
sel<='U';
when s1=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='0';
ir_enable<='0';
load_a<="UUU";
load_b<="UUU";
sel<='U';
when s2=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='0';
ir_enable<='1';
load_a<="UUU";
load_b<="UUU";
sel<='U';
when s3=>
pc_enable<='0';
alu_enable<='1';
rom_enable<='0';
reg_enable<='0';
ir_enable<='0';
load_a<="UUU";
load_b<="UUU";
sel<='U';
when s4=>
pc_enable<='0';
alu_enable<='1';
rom_enable<='0';
reg_enable<='0';
ir_enable<='0';
load_a<="UUU";
load_b<="UUU";
sel<='U';
when s5=>
pc_enable<='0';
alu_enable<='1';
rom_enable<='0';
reg_enable<='0';
ir_enable<='0';
load_a<="110";
load_b<="110";
sel<='0';
when s6=>
pc_enable<='0';
alu_enable<='1';
rom_enable<='0';
reg_enable<='0';
ir_enable<='0';
load_a<="UUU";
load_b<="UUU";
sel<='U';
when s7=>
pc_enable<='0';
alu_enable<='1';
rom_enable<='0';
reg_enable<='0';
ir_enable<='0';
load_a<="UUU";
load_b<="UUU";
sel<='U';
when s8=>
pc_enable<='0';
alu_enable<='1';
rom_enable<='0';
reg_enable<='0';
ir_enable<='0';
load_a<="UUU";
load_b<="UUU";
sel<='U';
when s9=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='1';
ir_enable<='0';
load_a<="110";
load_b<="UUU";
sel<='1';
when s10=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='1';
ir_enable<='0';
load_a<="101";
load_b<="UUU";
sel<='0';
when wa=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='1';
ir_enable<='0';
load_a<="110";
load_b<="UUU";
sel<='0';
when wb=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='1';
ir_enable<='0';
load_a<="UUU";
load_b<="110";
sel<='U';
when rab=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='1';
ir_enable<='0';
load_a<="101";
load_b<="101";
sel<='0';
when wab=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='1';
ir_enable<='0';
load_a<="110";
load_b<="110";
sel<='0';
when ra=>
pc_enable<='0';
alu_enable<='0';
rom_enable<='0';
reg_enable<='1';
ir_enable<='0';
load_a<="101";
load_b<="UUU";
sel<='U';
end case;
end process;
end behavioral;
