FinFET biasing IDS Vs Width

[pforpashya]

Hi,

I am trying to understand DC biasing in a paper having 2-stage LNA implemented using FinFET in 32nm.

The width mentioned of first stage cascode is 1µm and second stage is 2.4µm.

The DC currents are not mentioned but overall DC power is mentioned which is 12mW

so, assuming 6mW in first stage giving 6mA of current for VDD of 1.2Vapprox

To attain this current in first stage with Vgs-vt=0.2 width needs to be 30µm.
For finFET,

w=NFIN*2*HFin......n=no.of fins, Hfin is height of fin=65nm, w is width of fin
also, NF, NFIN are mentioned in FinFET model
NF=no.of fingers, NFIN=no.of fins in each finger

My question is does the author of paper mentions width of each finger as 1µm taking NF=30 and NFIN=8 and we get w=1µm
w=8*2*65nm=1µm
1µm*NF=30µm

or the overall width is 1µm (mean I don't need to take any fingers) but with this width it is not possible to get 6mA of current, am I correct?
Any comments are welcome.
If need further clarification, do let me know
Thnx in advance