# Finding the minimum value in Verilog. Given the C code and must turn to Verilog.

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#### Franci25

##### Newbie level 1 So my professor gave me this problem and no background what so ever on this subject. He just talked about it for 5 minutes in class and gave us this huge problem to solve. The one thing he said to do is a state machine. So far this is what i have come up with. So basically I have to use a state machine to turn this C code into verilog. I have to find the minimum value out of 4 values and it continuously does this. So every 4 values it displays the min value on the hex displays of the DE2 board. I am using notepad ++ for now to write my code. Once i have something to start with I will use Quartus to compile and run. Attachment is on the bottom for the problem description.
Code:
moduleExam3(max1,clk,rst,out,warning)

input [7:0]max1; //set max repetitions
input clk;
input rst;

output [6:0]out;
wire [6:0]out;
output warning;

parameter Start			= 4'd0;
parameter Initialize	        = 4'd1;
parameter CheckFor		= 4'd2;
parameter Sum1			= 4'd3;
parameter Sum1update	        = 4'd4;
parameter minvalue		= 4'd5;
parameter value2		        = 4'd6;
parameter Update		        = 4'd7;
parameter End			= 4'd8;
parameter danger		        = 4'd9;

reg [3:0]S;
reg [3:0]NS;
reg [7:0]sum;
reg [7:0]i;
reg warning;
reg [6:0] count;
reg [6:0]int_out;

always @ (posedge max1) begin
if(rst==1'bo)
begin
S <= Start;
end
else
begin
S <= NS;
end
end

always @ (posedge clk)
begin
case (S)
Start:
NS <= initialize;
initialize:
NS <= checkFor;
checkFor:
begin
if ( i >= max1)
NS <= End;
else
NS <= Sum1;
end
Sum1:
begin
if (count == i)
NS <= minvalue;
else
NS <= Sum1update;
end
Sum1update:
NS <= Sum1;
minvalue:
NS <= value2;
value2:
NS <= update;
update:
NS <= checkFor;
default:
NS <= danger;
endcase
end

always @ (posedge clk)
begin
case (S)
initialize:
being
sum = 1'b1;
i = 1'b1;
value = 2'd2;
value2 = 1'b101;

end
Sum1:
begin

[COLOR="#FF0000"]This is where i am stuck
[/COLOR]

//Seven seg display

assign out = int_out;
assign out = int_out;
assign out = int_out;
assign out = int_out;
assign out = int_out;
assign out = int_out;
assign out = int_out;

always @(*)
begin
if (rst == 1'b0)
int_out = 1'b0;
else
begin
case (sum)	    // abcdefg
4'h0: int_out = 7'b0000001;
4'h1: int_out = 7'b1001111;
4'h2: int_out = 7'b0010010;
4'h3: int_out = 7'b0000110;
4'h4: int_out = 7'b1001100;
4'h5: int_out = 7'b0100100;
4'h6: int_out = 7'b0100000;
4'h7: int_out = 7'b0001111;
4'h8: int_out = 7'b0000000;
4'h9: int_out = 7'b0000100;
4'ha: int_out = 7'b0001000;
4'hb: int_out = 7'b1100000;
4'hc: int_out = 7'b0110001;
4'hd: int_out = 7'b1000010;
4'he: int_out = 7'b0110000;
4'hf: int_out = 7'b0111000;
endcase
end
end
endmodule
View attachment ECE 287 Exam 3.pdf

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