[SOLVED] Finding path from Primary Inputs to a net in Design Compiler or PrimeTime

[anandhavel]

Hi,
If I specify a net in a verilog module, is it possible to find the primary inputs and path to the specified nets in either PrimeTime or DesignCompiler?

Thanks,
Anand

 

[englishdogg]

try all connected to that net and then fanin / all_fanin
Not sure of the exact command been a while since i used DC

 

[anandhavel]

Thanks for the help englishdogg.

I found that "report_transitive_fanin" works.