Finding Hold Time Violation through DC

[srinivasansreedharan]

Hi,
I read about finding hold time violation by giving set_input_delay 0 and set_output_delay 0. How do these help to find the hold time violation of a design?

 

[ljxpjpjljx]

do you try PT to have the timing report?

 

[srinivasansreedharan]

No. I just read about them in the Advanced ASIC Chip Synthesis book by Himanshu Bhatnagar. I understand the commands of input and output delay and the concept of hold time, but i dont understand how they report the hold time violation when they are set to 0

 

[kumar_eee]

When you set your input & output requirement, it does helps in both setup & hold analysis.

Lets wait for others comments also.