vipulsinha
Member level 2
Hello All ,
I am designing a module that has to run at 350MHz. I am in the architecture phase and would like to know how to figure out the possible frequency of operation of the design before entering the synthesis phase. Normally we have to wait till the synthesis to get an idea about the frequency of operation. I need a rough idea with 10-15% error margin.
What if the frequecncy fails to meet the requrement and the difference is very big and cannot be solved in the RTL optimization or syntheis techniques. This amounts to again visiting the High level design to figure out the bottlenecks .
I am interested in the techniques to find the rough idea of the frequency of operation in the early phase of the design to meet the frequency of demand if it is high speed design .
Secondly how to get a rough idea about the no of flops in the design before entering the synthesis phase.
sharing any handout or methodology followed will be highly appreciated.
THanks
Vips
I am designing a module that has to run at 350MHz. I am in the architecture phase and would like to know how to figure out the possible frequency of operation of the design before entering the synthesis phase. Normally we have to wait till the synthesis to get an idea about the frequency of operation. I need a rough idea with 10-15% error margin.
What if the frequecncy fails to meet the requrement and the difference is very big and cannot be solved in the RTL optimization or syntheis techniques. This amounts to again visiting the High level design to figure out the bottlenecks .
I am interested in the techniques to find the rough idea of the frequency of operation in the early phase of the design to meet the frequency of demand if it is high speed design .
Secondly how to get a rough idea about the no of flops in the design before entering the synthesis phase.
sharing any handout or methodology followed will be highly appreciated.
THanks
Vips