The only I know to apply some timing to gate simulation (according gate are the results of synthesis) is to back-annotate your netlist from sdf file (maybe some other file exists).
When you talked critical delay, you talked critical path?
During your course you should learn timing path are the result of gate delay, net delay, clock skew maybe. To have a net delay means the place and route has been done too.
At each stage of this flow, synthesis,place and route the tool used can give you a report for critical path.
It has more sense to define critical path with STA tools like PrimeTime than Modelsim.
I guess for a very small design you can see visually the critical path with modelsim but with a real design you can't there is too many path to check.
Regards
JErome