file read permission error inside Vivado

[promach]

I have problem with file read permission error inside Vivado, but it seems that none of the actual mentioned files had file read permission issues. I have attached the entire Vivado project as a compressed zip file.

Could anyone advise ?

See the console log : the path is not long, and there is no whitespace in the path, and the path is not empty string ""

test_ddr3_memory_controller.mem.cmd_task: at time 701958671.0 ps INFO: Initialization Sequence is complete
test_ddr3_memory_controller.mem.cmd_task: at time 703430100.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703432957.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703435814.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703438671.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703441528.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 703501528.0 ps INFO: Read      bank 3 col 000, auto precharge 1
test_ddr3_memory_controller.mem.read_from_file: at time 703514385.0 ps ERROR: fseek to           x failed
$finish called at time : 703514385 ps : File "/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.srcs/sources_1/imports/DDR/ddr3.v" Line 665
run: Time (s): cpu = 00:00:52 ; elapsed = 00:11:37 . Memory (MB): peak = 7663.180 ; gain = 2.137 ; free physical = 3865 ; free virtual = 10404

 

[FvM]

According to log, you are calling fseek() with unknown index value x. Messagebox "Unable to open file" suggests also that the filename is empty. You would want to check variable values during fopen and fseek action.

 

[promach]

It seems that row = row_pipeline[0]; contains the XXX value.

But I am not sure what causes this.

Note: According to the simulation waveform in the first post in this thread, there is no XXX value in any of the DDR command inputs signals