Hi,
I see three possible options:
1.) use a dual port memory (means a memory which has two access port, this is normally available in ASIC technologies) I think this is out of scope of the interview question
2.) access a singel port memory with double speed (so you can do two memory access during one fifo access) For this you would need a double clock or work on falling edge
3.) us a single memory which is 64x128k and add a latch logic at the input and output (this works because a fifo has no random access pattern, but a sequential access pattern) Take care if your application writes odd numbers of data into the fifo.
For curiosity:
How does the design look like if you use two memory. I see no advantages, because depending on the offest between read and write you may still need to read from the same memory
regards