FIFO depth and full condition

[sun_ray]

There is an asynchronous FIFO of depth 10. The FIFO write clock frequency is 10 MHZ and the read clock frequency is 60 MHz. The FIFO is being written at every write clock cycle and being read at every 6th clock of the read clock. When will the FIFO be full?

Thanks

 

[mathespbe]

Since u read the FIFO for every 6th cycle of 60MHZ clock the read operation, when u write a data, it reads it immediately with the same write interval. I guess the FIFO full condition 'll never occur...

 

[AdvaRes]

in 0.1µs (the period of the slowest clock) a single data is writen and read. So your fifo will never be full even if it was of 1 depth.

 

[mathespbe]

There may be a chance of getting FIFO full condition if the depth is 1. Because the write and read operation shoud takes place in the consecutive clock cycles here. At the end of write cycle for(for 1 clk period) the FIFO full condition might occur. If the depth is 2 or greater thn 2 the FIFO full condition 'll never occur....

 

[Venkadesh_M]

There may be a chance of getting FIFO full condition if the depth is 1. Because the write and read operation shoud takes place in the consecutive clock cycles here. At the end of write cycle for(for 1 clk period) the FIFO full condition might occur. If the depth is 2 or greater thn 2 the FIFO full condition 'll never occur....

what if the FIFO already have 10 datas ?