Syswip
Advanced Member level 4
Hi forum,
Do we really need to scale FFT for hardware implementation?
Up to now I found 2 situations where scaling has advantage:
1. It will save the logic because the internal word length remains unchanged.
2. The twiddle factor multiplication error will be less.
The scaling also can be required if the output word length must be equal to the input word length. In this case I have a 2 choices:
1. Do not scale (increase word length after each stage) and at the end shift the result right by the corresponding value.
2. Use scaling.
How to make the choice if I don't care about gate counts?
Does the scaling significantly decrease the FFT error?
Thank you very much,
Tiksan.
Do we really need to scale FFT for hardware implementation?
Up to now I found 2 situations where scaling has advantage:
1. It will save the logic because the internal word length remains unchanged.
2. The twiddle factor multiplication error will be less.
The scaling also can be required if the output word length must be equal to the input word length. In this case I have a 2 choices:
1. Do not scale (increase word length after each stage) and at the end shift the result right by the corresponding value.
2. Use scaling.
How to make the choice if I don't care about gate counts?
Does the scaling significantly decrease the FFT error?
Thank you very much,
Tiksan.
