mohamed_shfat
Newbie level 4
Greetings all
I'm here new to the FPGA world and the HDL as well, i'm trying to implement some FFT core function on my Arty 7 FPGA board used the verilog language, but unfortunately i'm facing a lot of problems to control this core and make it work successfully.
My question here is about the data_valid line of the input of the FFT core v9.0 , how can i design or control this line with a good way so it allows the data to be streamed to the core. Can I for example make it always high data_valid =1 because i'm using a real time processor and getting the data from the XADC, or there is another way? Or is there any ready state machine design to control this FFT core?
Please if someone can help me i would really appreciate the help too much.
Regards
Mohamed
I'm here new to the FPGA world and the HDL as well, i'm trying to implement some FFT core function on my Arty 7 FPGA board used the verilog language, but unfortunately i'm facing a lot of problems to control this core and make it work successfully.
My question here is about the data_valid line of the input of the FFT core v9.0 , how can i design or control this line with a good way so it allows the data to be streamed to the core. Can I for example make it always high data_valid =1 because i'm using a real time processor and getting the data from the XADC, or there is another way? Or is there any ready state machine design to control this FFT core?
Please if someone can help me i would really appreciate the help too much.
Regards
Mohamed