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FET OpAmp input stage

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fala

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op amp input stage

Hello board, the following circuit has been taken from input stage of FET opamps. It should work but it dose not! not in spice smulation and not even in hardware prototype. Q15 works as constant current source and it has been intended to draw its current from Q4 & Q5 but what actually happens both in simulation and both in hardware prototype, it makes Q12 & Q6 gate-source junction forward biased and it draws current from inputs! what mistake I made?
can someone help me?


Thanks alot!
 

rajanarender_suram

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might be you have not taken care of DC biasing at the gates of Q12 and Q6
 

fala

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Hello suram, thanks for the reply but paramount charactristic of FET opamps is their low bias current and because of that they can't bias gate of input JFETs with resistors(some of them use protection diodes which is not DC biasing) I post a schematic of a FET opamp.
89_1186817838.jpg

and the whole datasheet link is:
https://eshop.engineering.uiowa.edu/NI/pdfs/00/55/DS005557.pdf
Thanks a lot.
 

kwkam

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you are missing a 100K resistor connect from VCC to Q15 base.
 

    fala

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fala

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Thanks a lot kwkam, problem as you pointed out was zenner diode biasing. Now in simulation I do not have forward biasing I will check hardware prototype. but can you please tell me what makes Q6 and Q12 to remain reversed biased ? surely still Q6 and Q12 can go forward biased and provide current requirement of Q15 through their inputs rather than stay reverse biased and provide this current through Q4 & Q5? I think if I understand the answer to this question I can prevent forward biasing to happen in some odd situations.
Thanks a lot for your help.
 

kwkam

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I don't know what are you talking about. For a differential pair, Q6 and Q12 must be forward biased. You have to claim Vds ~3V to keep NJFET in linear range.
 

    fala

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fala

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sorry kwkam I was not very clear, form forward biasing I mean gate source junction diode which should be reversed biased Q15 can draw current from Q6 and Q12 source gate diodes by making them forward biased. what prevent Q15 to make source-gate diodes of Q6 and Q12 forward biased and force it to draw current from Q4 & Q5 by reverse biasing Q6 and Q12 gate-source diodes?
Again sorry for the ambiguity but because my brain is so much occupied with forward biasing of gate-source diode I mistakenly referred to forward biasing of the JFETs.
Thanks a lot
 

kwkam

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Do you know what is JFET!? Vgs of NJFET always -ve in differential pair balanced condition. You better read more books before config any circuit. Linear circuit is much difficult than digital.
 

kwkam

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Do you know what is JFET!? Vgs of NJFET always -ve in differential pair balanced condition. You better read more books before config any circuit. Linear circuit is must difficult than digital.

Added after 5 seconds:

Do you know what is JFET!? Vgs of NJFET always -ve in differential pair balanced condition. You better read more books before config any circuit. Linear circuit is much difficult than digital.
 

fala

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kwkam, of course I know what JFETs are. I want to know why vgs is always negative in differential pair balanced condition. I have not read anything about this kind of biasng in my text books(e.g. Electronic devices and circuit theory Robet L.Boylestad & and louis Nashelsky 2006 edition) if you know a resource that expain this kind of biasing please refer me to it. what is -ve?
 

kwkam

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JFET require -ve Vgs to turn-off the device. The physics of JFET can find in google
 

fala

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kwkam, your notation is not standard what -ve stands for do you mean -Vee? I have not seen this notation in the entire FET sections of my textbook, how do you expect me to understand your non standard notation by searching google? meanwhile I could not found any material in google that explains "differential pair balanced condition" in google, where you read about it ? is it so hard to type the name of a reference?
regards,
 

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