FET frequency multiplier biasing for input below 0dBm (make DC load line very steep)

[Terminator3]

How far i can go with that? Idea is to decrease biasing resistor values (Rd and Rs), keeping Q point at 0mA acting as class-B amplifier to generate harmonics from weak signal. As DC load line becomes steeper, Drain Current becomes bigger with same amount of input signal, and exceed RECOMMENDED OPERATING CONDITIONS of datasheet. class-B amplifier must take a rest 50% of time (less temperature, other effects maybe..), so the question is how much i can go above recommended drain current value?

 

[vfone]

You cannot go above recommended current drain value even in class-B operation.

 

[Terminator3]

If still go above, what kind of failure it will be? Temperature degradation or breakdown?

 

[vfone]

From both, because will be an avalanche failure. Initially will be a breakdown followed by temperature degradation.
Is a common failure for FETs used in switching power supplies.