I've seen this exact error before, but don't recall what code I change to get around it. As I recall it had something to do with the tool not knowing how to handle some of my code (which is/was valid Verilog code) I ended up having to re-code the file in a different way to get rid of the problem. I suspect the problem has to do with ISE's parser. Vivado could and did compile the same file without a problem (different synthesis parser) but I couldn't switch to Vivado at the time.
Remove any Verilog beyond 2001 and/or VHDL beyond 1993 (or maybe 2002) and try compiling the file again. Or switch to Altera, Quartus-II support for more recent versions of the language standards is much better than Xilinx.