fatal_error : simulator: fuse.cpp : 209:1.133

[Furqan Ghoghari]

I keep getting this error in every VHDL code I make in Xilinx ISE Design Suite 14.5,even in the smallest codes which were simulating earlier but now shows error mentioned below.I have tried everything- searched through the internet and xilinx forums,re-installed xilinx a number of times(by trying different softwares) and much more but could not get a working solution to it. Please if anyone knows anything about this error, do suggest.

I have spent a lot of time searching for the solution, asked friends and proffesor but could not find it. So, please it is a humble request that if anyone knows even a slight thing about it,please help.

This is the error:

FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files. Please recompile with -mt off -v 1 switch to identify which design unit failed. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.

I have also compiled with -my off -v 1 but it ended with showing an another error as follows :

FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/precompiled.exe.sim/ieee/p_2592010699.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.

I have searchred on xilinx forums and tried many solutions even I installed gnu GCC compiler but still I am receiving same errors. What should I do now?

I have seen your conversatios with ayush15 but i didn't find any proper solution please give me the proper solution as early as possible.

 

[dpaul]

In my opinion this is a very specific ISE software error. The Xilinx forums might be the only place where you may find something......keep trying!
In parallel did you try to simulate your design using WebPACK Edition of the Vivado Design Suite (try it out if not done)?

 

[ads-ee]

I've seen this exact error before, but don't recall what code I change to get around it. As I recall it had something to do with the tool not knowing how to handle some of my code (which is/was valid Verilog code) I ended up having to re-code the file in a different way to get rid of the problem. I suspect the problem has to do with ISE's parser. Vivado could and did compile the same file without a problem (different synthesis parser) but I couldn't switch to Vivado at the time.

Remove any Verilog beyond 2001 and/or VHDL beyond 1993 (or maybe 2002) and try compiling the file again. Or switch to Altera, Quartus-II support for more recent versions of the language standards is much better than Xilinx.

 

[TrickyDicky]

Remove any Verilog beyond 2001 and/or VHDL beyond 1993 (or maybe 2002) and try compiling the file again. Or switch to Altera, Quartus-II support for more recent versions of the language standards is much better than Xilinx.

Vivado 2015 has better 2008 support than Quartus!