emmos
Member level 2
hello
I am writing a vhdl program for reading text files and i run it in modelsim but it gives me the following error
** Error: (vsim-7) Failed to open VHDL file "hds_projects/my_project2/my_project2_lib/hdl/file_io.txt" in rb mode.
# No such file or directory. (errno = ENOENT)
why???
plz help
i attached the vhdl code
thanks
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY std;
USE std.TEXTIO.all;
ENTITY file_io IS
END ENTITY file_io;
--
ARCHITECTURE test OF file_io IS
signal done : std_logic := '0'; -- flag set when simulation finished
begin -- test of file_io
done <= '1' after 5 sec; -- probably set via logic, not time
read_file:
process -- read file_io.in (one time at start of simulation)
file my_input : TEXT open READ_MODE is "hds_projects/my_project2/my_project2_lib/hdl/file_io.txt";
variable my_line : LINE;
variable my_input_line : LINE;
begin
write(my_line, string'("reading file"));
writeline(output, my_line);
loop
exit when endfile(my_input);
readline(my_input, my_input_line);
-- process input, possibly set up signals or arrays
writeline(output, my_input_line); -- optional, write to std out
end loop;
wait; -- one shot at time zero,
end process read_file;
write_file:
process (done) is -- write file_io.out (when done goes to '1')
file my_output : TEXT open WRITE_MODE is "hds_projects/my_project2/my_project2_lib/hdl/file_o.txt";
-- above declaration should be in architecture declarations for multiple
variable my_line : LINE;
variable my_output_line : LINE;
begin
if done='1' then
write(my_line, string'("writing file"));
writeline(output, my_line);
write(my_output_line, string'("output from file_io.vhdl"));
writeline(my_output, my_output_line);
-- write(my_output_line, done); -- or any other stuff
writeline(my_output, my_output_line);
end if;
end process write_file;
END ARCHITECTURE test;
I am writing a vhdl program for reading text files and i run it in modelsim but it gives me the following error
** Error: (vsim-7) Failed to open VHDL file "hds_projects/my_project2/my_project2_lib/hdl/file_io.txt" in rb mode.
# No such file or directory. (errno = ENOENT)
why???
plz help
i attached the vhdl code
thanks
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY std;
USE std.TEXTIO.all;
ENTITY file_io IS
END ENTITY file_io;
--
ARCHITECTURE test OF file_io IS
signal done : std_logic := '0'; -- flag set when simulation finished
begin -- test of file_io
done <= '1' after 5 sec; -- probably set via logic, not time
read_file:
process -- read file_io.in (one time at start of simulation)
file my_input : TEXT open READ_MODE is "hds_projects/my_project2/my_project2_lib/hdl/file_io.txt";
variable my_line : LINE;
variable my_input_line : LINE;
begin
write(my_line, string'("reading file"));
writeline(output, my_line);
loop
exit when endfile(my_input);
readline(my_input, my_input_line);
-- process input, possibly set up signals or arrays
writeline(output, my_input_line); -- optional, write to std out
end loop;
wait; -- one shot at time zero,
end process read_file;
write_file:
process (done) is -- write file_io.out (when done goes to '1')
file my_output : TEXT open WRITE_MODE is "hds_projects/my_project2/my_project2_lib/hdl/file_o.txt";
-- above declaration should be in architecture declarations for multiple
variable my_line : LINE;
variable my_output_line : LINE;
begin
if done='1' then
write(my_line, string'("writing file"));
writeline(output, my_line);
write(my_output_line, string'("output from file_io.vhdl"));
writeline(my_output, my_output_line);
-- write(my_output_line, done); -- or any other stuff
writeline(my_output, my_output_line);
end if;
end process write_file;
END ARCHITECTURE test;