Fast Passive Parallel FPGA configuration through Parallel Flash Loader IP.

[di_i]

Hi!

There is a Cyclone 4 Development Board. MAX II CPLD is on the board.
My purpose is to configure Cyclone 4 FPGA through Parallel Flash Loader (PFL) that is inside MAX II in Fast Passive Parallel Mode (FPP).
My steps are following:

- Attach specified .pof file to MAX II CPLD that is in Quartus Programmer JTAG chain.
- Attach flash device to MAX II CPLD.
- Specify the correct flash .pof file that contains Cyclone 4 FPGA image as a flash device connected to MAX II.
- Set up Program/Configure field.
- Press "Start" to configure system.

MAX II CPLD is managed to be configured. When flash is being programed the following message to be shown:

Info (209018): Device 1 silicon ID is not ready - waiting for pfl_flash_access_granted to be asserted
Info (209018): Device 1 silicon ID is not ready - waiting for pfl_flash_access_granted to be asserted
Info (209018): Device 1 silicon ID is not ready - waiting for pfl_flash_access_granted to be asserted

......................................................................................................................................

Info (209018): Device 1 silicon ID is not ready - waiting for pfl_flash_access_granted to be asserted
Info (209018): Device 1 silicon ID is not ready - waiting for pfl_flash_access_granted to be asserted
Error (209064): Failed to get access to the flash interface
Error (209012): Operation failed


I can't to find anywhere what does this message mean.
Please, help me to find out how to resolve it.

Thank you in advance!

 

[FvM]

The message says that the PFL IP input signal pfl_flash_access_granted isn't set. It's a handshake signal for applications where PFL isn't exclusively controlling the flash. It will be normally tied to '1'.

 

[di_i]

So, the way to resolve it is to set pfl_flash_access_granted to "1", isn't it?