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falling edge of clock to sample data bit at centre

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Jan 12, 2005
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16x data rate clock in uart

Hi all,

i have a clock capable of generating freq of 10khz to 16.7khz.I need to get the clock to synchronize with the serial data bits. Following the start bit for a RS232 data frame,Each data bit is sampled at its centre until the stop bit is encountered.

Qn1. Can i use a Digital Phase lock loop to achieve this? what PLL chip is suitable

Qn2.How do i connect up the pins on the PLL chip such that the data and the clock are synchronized together?

see attachment for the desired timing diagram


start bit sampling data


I'm sure you are aware of the conventional way of correctly receiving a byte packet with start and stop. Oversampling (8x or 16x) the datarate, and once the falling edge of the start bit is detected, the receiver waits 1/2 the bit-time (so, if you oversample by 16x, you wait 8 clocks). This way, you are looking in the middle of the start bit. You then simply delay the clock 16x, so you 'look' or 'sample' at the middle of the first bit.

I've done that method myself many times in logic, and its pretty damn reliable, so long as both clocks at the Tx and Rx are within 5% of each other.

Anyway, if you are planning on receiving packets at a variable, or unknown bitrate then maybe a PLL would be best. I personally tend to avoid them, because I don't have much experience with them, and I can generally do it all in pure logic (using counters, shift-registers etc..).

One thing though, looking at your diagram, I assume you are trying to 'syncronise' your clock with the incoming data instantly. By that, I mean without 'training' the PLL. In most cases, the first part of a packet you send, when using a PLL in the receiver, is a 'preamble'. Its usually for 'radio' links, but it also trains the PLL for the incoming datarate, allowing it to 'lock-on' before any real useful data arrives.

So, seeing as its christmas :D I'll try and be of some use.

Q1. You can use a DPLL of course! But, it all depends on costs, the datarate of the system (variable, fixed, high, low etc...) and how complicatied you wish to make it. Using a PLL will require you to send a few 'dummy' packets as a training sequence, like 10101010.

A 'suitable' chip? As I said, I don't really know about PLL's, but I've used this once, with great success:

And its a 74 series logic chip, cheap and easy to get hold of. Also, theres plenty of reference designs for this IC on the web. It has a built-in VCO, that is tuned by external components up to 12Mhz.

Q2. The datasheet should get you started on a basic design. But read carefully about 'lock-times', that will tell you have many 'packets' you'll have to send, before you can start receiving data reliably (ie: not garbage).

There you go, I would strongly recomend the 'oversampling' idea, if its suitable. You'll 'lock-on' to the data instantly, at the start bit, and you can always use this setup to output a clock, just like in your diagram. A microcontroller, CPLD, FPGA, even a PAL could do it.

Hope this helps, good luck.


bit sampling start bit

hi buriedcode and all

thanks for the information. I think it keeps me informed and started on how to get about the problem.

Qn1: So besides having the PLL IC,do i need additional ICs or components.( shift register/counters)? By just using the PLL IC you recommended,it will do the trick?

Qn2: Correct me if i am RS232 data baud rate is set at i need to input the data into 1 pin of the IC chip, and also the clock into another pin.
At the output of the IC,will i achieve the output i desired as specified in the schematic( i uploaded)

falling edge of clock finnish

Hi again,

I forgot to mention that what you are trying to do is a classical example of a UART (universal asynchronous receiver transmitter). Type it into google if you don't know what it is.

I don't know what level of electronics skilll you are at, and I don't want to tell you things you already know. Please tell us what this 'IC' is that the data is going into? If all you need is clock recovery then there are a few UART chips available, but you'll just need the 'receiver' part. I personally think a PLL is a complicated way to go.

For this sort of thing (UART, RS232) there are many ways to correctly receive a signal. Pure logic, PLL, UART IC, or a microcontroller. Most microcontrollers have built-in UARTS that just need to be configured for correct datarate, plus, because they are so common, they are probably one of the cheapest solutions. So long as you have basic programming skills (assembly mainly).

So, my questions are:
What is the application?
Is this connected to a PC in any way?
Are you using any form of computational logic (microcontrollers, DSP, etc.)
Or are you using pure logic (logic gates, like CMOS, TTL, 74 series etc..)

In answer to your questions.

q1) I think a PLL alone may do it. But as I said, this must first be trained before each packet. So if you send 8 bytes consecutively (one after the other) the first 1-3 will be lost, and are simply used to get the PLL to 'lock'. IMO, its not the easiest, or cheapest way to go.

Correct me if i am RS232 data baud rate is set at i need to input the data into 1 pin of the IC chip, and also the clock into another pin.

RS232 can have any baud really. Generally the standard ones are 2400, 4800, 9600, 19200 etc.. If you use a specific IC (like a UART chip) then it will require a clock many times this frequency, to 'over-sample' the incoming data. When you say 'IC', do you mean the PLL? or the chip that the information is for?

I'm sorry for all the questions, I'm just not familliar with using a PLL to recover UART data. There are so many 'UARTs' about now, in various chips, that few people use PLL's anymore. I'll try and be of more use next post.


hi buriedcode and all,

I have included a full summary attachment of my project..and what i have come up with so far for the software part.

P.S: i will prefer to do it in pure logic for the hardware if possible because i am not very familar with microcontroller and PLL..

hpe you can guide me along as i do encounter difficulty in implementing the hardware interface.

thanks a lot

Hi buriedCode,

Correct me if I am wrong.

1. If I send the string “1CF01C” for ASCII character ‘a’ from the 1st PC, will I be sending the correct sequence of bits from LSB to MSB so that the keyboard controller at the 2nd PC will treat the string as a set of scancode?

2. If I do set the baud to be between10kbps-20kbps from the PC software, I will then be able to generate RS232 data at a rate similar to a typical keyboard clock frequency. If the data is passed through a MAX232 chip, it can then be converted it into a TTL/CMOS 0-+5v data to be used as keyboard data. Is my concept so far correct?

3. So at this stage, my main concern is to synchronize the PS/2 clock to the data so that they can be transmitted and correctly interpreted by the keyboard controller at the 2nd PC?

Thanks a lot

P.S: thanks for following up my messages.I am quite lost in fact with the hardware design


Hi buriedcode,

Thanks for helping me out. I am quite weak in hardware design especially when concerned with FFs.

Qn1: what is timer overflow about?

Quote: Once the timer over-flows, the 'oscillator' mentioned above, is reset,
and at the same time, connected to the clock line on the PS/2.

Qn2: Is the timer a sampling counter to sample each data bit at its centre? We have to set the timer at ½ of the bit time? I am quite confused.I thought we need to oversample the oscillator to about 2 times the frequency of the RS232 data

Quote: The timer starts as soon as there is a change in line state, like 1->0,
the begining of the start bit. This timer is set to 1/2 of the bit time.

P.S: with the schematic u are coming up with, i am sure most of my doubts will be cleared


Hi buriedCode,

I know i shdnt be spoonfeed and as such, i came up with my own undestanding of what you have told me so far.

i need an oscilator which runs at 2.4576Mhz.This will go through a divider circuit (/128) to give a frequency twice as much as the freq of the data.

I will have a binary counter/timer that starts as soon as 1->0 transition(beginning of start bit).Set the timer to 1/2 bit time(i.e:52.1us) first to sample at the middle of the start bit.This requires a 64-bit up-counter and a clk freq of 1Mhz.

Once the timer overflows,oscillator clock is reset and at the same time connected to the clk line on PS/2.Now we are looking at the middle of the start bit.Then we will set timer to delay one whole bit period for subsequent 10 bits?

Next, we use a up-counter to keep track of how many bits have been sent.
Once finished reading the 11th bit,reset timer.The timer will resume when the next start bit of the next frame arrives.

P.S: i am able to understand some of the points u mentioned,butI have a problem with trying to translate those ideas into pure logic.It will be clearer if i could catch and anaylse a schematic from you.I will definitely be able to visualize better in that case.

Take care.

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