rbmaze
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I am trying to understand what is causing the negative overshoot of my 16 MHz clock signal. Basically my confusion is about the flow of current vs the direction of wave travel. When the clock generates a falling edge the current is flowing towards the source, but the wave is still propagating towards the load. Please see my simple bounce diagram.
My two ideas of what is happening are as follow. 1) The negative overshoot is caused by reflections at the load, just the same as positive overshoot. or 2) the negative overshoot is caused by reflections at the source, since current flow is opposite of a rising edge. I think the answer is 1, and details of what I think is happening are below. Can anyone please confirm my thinking is correct? Thank you!
Vpp of my clock is 3.3V. Is my source essentially -3.3V at t= 0? Prior to t=1T, the load is in a steady state of approx. 3.3V.
Between t=0 and t=1T, the -3.3V wave propagates towards the load. Once at the load, the output voltage is 3.3V (steady state) + (V1+) + (V1-) ~= 3.3 - 3.3 - (3.3*reflection coeff). This is where the negative overshoot comes from (V1-).
My two ideas of what is happening are as follow. 1) The negative overshoot is caused by reflections at the load, just the same as positive overshoot. or 2) the negative overshoot is caused by reflections at the source, since current flow is opposite of a rising edge. I think the answer is 1, and details of what I think is happening are below. Can anyone please confirm my thinking is correct? Thank you!
Vpp of my clock is 3.3V. Is my source essentially -3.3V at t= 0? Prior to t=1T, the load is in a steady state of approx. 3.3V.
Between t=0 and t=1T, the -3.3V wave propagates towards the load. Once at the load, the output voltage is 3.3V (steady state) + (V1+) + (V1-) ~= 3.3 - 3.3 - (3.3*reflection coeff). This is where the negative overshoot comes from (V1-).