"Failed to Simulate" Issue in Virtuoso AMS

[johnnyfan]

Hi all,

This is my very first post on this forum. The version type is Cadence Virtuoso 6.1.5.

I try to use virtuoso ams to simulate a sar adc circuit. Everything worked fine when I used veriloga blocks to run the simulation. But an issue came when I changed the DAC block into schematic view.

I have updated the Library List and it compiled successfully, elaborated successfully. Then it just stuck at "Failed to Simulate". And I could not find the reason from log file.

Do anyone has any idea what cause this issue? I have attached the snapshot of my log file below. Please check. Thanks a lot!

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module SAR_ADC_Veriloga.combine_test:schematic (up-to-date)
        errors: 0, warnings: 0
ncvlog: Memory Usage - 9.7M program + 19.3M data = 28.9M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.1s, 38.9% cpu)
Successfully compiled ('SAR_ADC_Veriloga' 'combine_test' 'schematic').
Compilation successful.
ncelab(64): 08.20-s019: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
    Elaborating the design hierarchy:
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
"/proj/cad/library/mosis/GF65_LPe/EDA-CAD-65N-DK012_rev3/ch65lpe_alt_DK012_OA_Rev3/6_00_01_00_LB/ch65lpe_alt/../models/YI-SM00034/1C/sm00034-1c.scs", line 39: 
    Illegal library definition found in netlist
 
    Discipline resolution Pass...
    Building instance overlay tables: .................... Done
    Loading native compiled code:     .................... Done
    Building instance specific data structures.
    Design hierarchy summary:
                         Instances  Unique
        Modules:                26       9
        Registers:              30      10
        Scalar wires:           13       -
        Expanded wires:          8       1
        Vectored wires:          4       -
        Always blocks:          29       9
        Initial blocks:         12       2
        Cont. assignments:      11       3
        Interconnect:           33       -
        Simulation timescale:  1ps
    Equivalent connect instance summary:
    1: combine_test.I17
    2: combine_test.I13
    3: combine_test.I12
    4: combine_test.I11
    5: combine_test.I10
    6: combine_test.I9
    7: combine_test.I8
    8: combine_test.I7
    9: combine_test.I6
    10: combine_test.I16
    11: combine_test.I15
    12: combine_test.I14
    Writing initial simulation snapshot: SAR_ADC_Veriloga.combine_test:config
    Elaborating analog portion of the design hierarchy:
        libsyracuse:  @(#)$CDS: libsyracuse version   11/15/2009 22:11 (chfclx007) $(sub-version  1115  )
ncelab: Memory Usage - 24.1M program + 756.2M data = 780.3M total
ncelab: CPU Usage - 0.3s system + 1.3s user = 1.6s total (3.9s, 40.4% cpu)
Successfully elaborated ("SAR_ADC_Veriloga" "combine_test" "config").
ncsim(64): 08.20-s019: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
Failed to simulate ("SAR_ADC_Veriloga" "combine_test" "config").
txe(64): 08.20-s019: (c) Copyright 1995-2008 Cadence Design Systems, Inc.

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