Fail-safe circuit in an LVDS Receiver

Status
Not open for further replies.
M

malikmunish

Newbie level 4
Joined
Sep 29, 2006
Messages
6
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,314
How can one implement Fail-Safe circuit for LVDS Receiver which is directly coupled. There are fail-safe circuits found for the receiver that is capacitively coupled. But, our requirement is fail-safe circuit for LVDS Receiver without capacitive coupling.

OR

Can anyone tell how to detect a zero differential signal received by the LVDS Receiver, while detecting random LVDS data?
 

I don't know if you have something about it: For RS485 you use a bias circuit. Just a resistor from VCC to input, resistor (562?) between input/inv. input(130 ?, terminator) and a resistor (562?) from GND to inv.input

In this link they have an example of a failsafe LVDS Receiver.
**broken link removed** (page 3-4)
 

the latter question depends on your comparator structure in the receiver - if you have a receiver which respects the hysteresis requirements of ieee1594 then you might adapt from that some kind of window comparator funtion which will alow you to detect a zero diff signal ...

at least this is one way to do it ...
 

Fail-safe is used to detect High-Z state, I think you can use a pull_up RES, and design a circuit that when the input commod voltage is bigger than SPEC,the output is high.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…