extraction of synthesizable code from given code

[snehalkate]

Is there any software or tool with which i can separate out synthesizable and non sythesizable code from a given verilog code?

 

[shaiko]

Is there any software or tool with which i can separate out synthesizable and non sythesizable code from a given verilog code?

I'm pretty sure that there's no such thing.
The ability to tell which code can or cannot be synthesized to real logic is an integral ability of any synthesis tool - once the tool sees something "illegal" the implementation process stops with an error.
It certainly doesn't separate synthesizable and non synthesizable logic apart - this is your job.

 

[sharath666]

Go through the warnings in the synthesis log to find out issues if any..That should be a good way to find out what is happening to your design..