Thank you freebird for your answer
it is useful to me to know that PPLUS for the PMOS or the NPLUS for the NMOS has no effct on the silicon, in this way I can avoid the minimum space DRC between these layers by merging them, hence optimizing layout area.
I have a further quesion,
In the technology I am using there is no NDIFF or PDIFF, there is only one layer of Diffusion, and I think the diffusion is then defined by the PPLUS or NPLUS, that is what I am thinking, then in my opinion this layer should cover the diffusion area only, why it is extended in the out region of the diffsion ?
Best Regards