parthiv2eng
Member level 2
That looks better. I think you may not be getting the best out of the logic analyser - I looked up the specification and it can sample at 25MHz.
Keith
Thanks Keith..Now, I am getting good output. But still have problem with CS line. Check below pic. It goes high before 5 byte transfer. Any clue?
![20120604_104846.jpg 20120604_104846.jpg](https://www.edaboard.com/data/attachments/20/20460-b708313c3f6d059ee97633b0ce8da217.jpg)
The B0 supposed to go high after compete transfer. But it won't.