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I did the layout of some standard cells using spice netlist. Procedure i followed was drawn the stic diagram first & then the layout by using layout editor tool.
As i read, after drawing the layout which is DRC & LVS clear we will charecterise to know other parameters which are stored in library when this is used as reference library for design.
My question is...
1.In which step we extract spice netlist?
2. Suppose if i want to design a library for 0.65u technology how to proceed?
3. How to include all the things such as rise time, fall time , capacitance, resistance for cell which is used for synthesis & physical design.
1. Spec from Customer
2. we do some basic analysis(rise time, fall time & pn ratio) to meet the spec.
3. get the approval from the customer
4. circuit design ( schematic, symbol & verilog)
5. Layout Design
6. Physical verification(DRC/LVS)
7. View Validation for Layout, schematic, symbol & verilog to ensure the quality.
8. Lib characterization ( .lib , fastscan, celtic & other view generation)
9. View Validation for the views generated by charact'z team.
10.Sign off & delivery to the customer.
Now coming to your Questions.
1. We extract the parasitics before the Characterization work starts.
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