raka200
Member level 2
Hi everybody !!!
I'm looking at a xilinx appnote, XAPP617.
There is a few lines that are quite a mistery to myself :
REC_CLK and NREC_CLK are two clock generated by DCM with 180° phase shift.
I understand the metastability stuff, (double sample ),
but I don't understand the second process with the trick to change the clock domain, with the comment cycle steal...
Why do we need this process ?
Why using a latch trigered by clock state, and not falling_edge ??? (target : virtex II pro)
thanks in advance...
I'm looking at a xilinx appnote, XAPP617.
There is a few lines that are quite a mistery to myself :
REC_CLK and NREC_CLK are two clock generated by DCM with 180° phase shift.
Code:
-- Capture potential first bit data, double sampling to remove metastability
PROCESS (NREC_CLK, XRESET)
BEGIN
IF (XRESET = '0') THEN
FQ <= (others=>'0');
ELSIF rising_edge(NREC_CLK) THEN
FQ <= DF;
END IF;
END PROCESS;
-- Move falling edge samples into the rising edge clock domain using latches (cycle steal)
PROCESS (NREC_CLK, FQ, XRESET)
BEGIN
IF (XRESET = '0') THEN
FL <= (others=>'0');
ELSE
IF (NOT NREC_CLK = '1') THEN
FL <= FQ;
END IF;
END IF;
END PROCESS;
-- FL metastability flops
PROCESS (REC_CLK, XRESET)
BEGIN
IF (XRESET = '0') THEN
FO <= (others=>'0');
ELSIF rising_edge(REC_CLK) THEN
FO <= FL XOR "01010101";
END IF;
END PROCESS;
but I don't understand the second process with the trick to change the clock domain, with the comment cycle steal...
Why do we need this process ?
Why using a latch trigered by clock state, and not falling_edge ??? (target : virtex II pro)
thanks in advance...