srinivasansreedharan
Junior Member level 3
Hi ,
I understand the definitions of set up and hold time. I would like to know what exactly happens in a flip-flop at gate level when set up and hold times are violated? Also any useful and detailed explanation of setup and hold time violation with respect to ASIC design will be appreciated.
I understand the definitions of set up and hold time. I would like to know what exactly happens in a flip-flop at gate level when set up and hold times are violated? Also any useful and detailed explanation of setup and hold time violation with respect to ASIC design will be appreciated.