Explanation of Setup and Hold Time

[srinivasansreedharan]

Hi ,
I understand the definitions of set up and hold time. I would like to know what exactly happens in a flip-flop at gate level when set up and hold times are violated? Also any useful and detailed explanation of setup and hold time violation with respect to ASIC design will be appreciated.

 

[rfcn]

Re: Set up and Hold Time

Hi ,
I understand the definitions of set up and hold time. I would like to know what exactly happens in a flip-flop at gate level when set up and hold times are violated? Also any useful and detailed explanation of setup and hold time violation with respect to ASIC design will be appreciated.

Any clock can't be ideal clock in real case. It must has more or less jitter. This means the edges of a clock may be a little bit earlier or later than the ideal ones. So if the the setup and hold time are violated, the output maybe wrong.

regards,
rfcn

 

[alaparthi]

Re: Set up and Hold Time

flip-flop needs certain time to charge/discharge the output node to the required voltage level. During this time, if there is a transition in the input, the output will be metastable. It is not full logic level.

Flip flop is normally made - NAND-NAND or NOR-NOR Configuration (Circuit level)
Understanding this operation really gives good insight into flop functionality.
Imagine two switches (ON/OFF) connected in series.

In ASIC point of you, a signal being unknown for some time, will propagate unknowns in the design and even if it settles to some value (1 or 0), this may not be correct value for the functionality. The circuits behave randomly.
Designer wants the circuit to be in know state.

Imagine having 10000s of flops in chips, randomness causes lots of issues.

So to avoid, metastability, the timing has to be met. Absolutely, No setup and hold violations.

 

[friend_333]

Re: Set up and Hold Time

I hope this can help you understand this clearly

Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.
Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability

If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.