Re: Set up and Hold Time
flip-flop needs certain time to charge/discharge the output node to the required voltage level. During this time, if there is a transition in the input, the output will be metastable. It is not full logic level.
Flip flop is normally made - NAND-NAND or NOR-NOR Configuration (Circuit level)
Understanding this operation really gives good insight into flop functionality.
Imagine two switches (ON/OFF) connected in series.
In ASIC point of you, a signal being unknown for some time, will propagate unknowns in the design and even if it settles to some value (1 or 0), this may not be correct value for the functionality. The circuits behave randomly.
Designer wants the circuit to be in know state.
Imagine having 10000s of flops in chips, randomness causes lots of issues.
So to avoid, metastability, the timing has to be met. Absolutely, No setup and hold violations.