Explanation needed for the attached circuit.

[the_falcon]

Hi all,
I would like to know the detailed operation of the comparator schematic(Fig. 2) in the attached article.Any voluntary help will be a big deal for me.Thanks so much people..

Falcon

 

[erikl]

I would like to know the detailed operation of the comparator schematic (Fig. 2) in the attached article.

I'd think it is quite well explained in the paper on p. 2 . Any special questions?

 

[the_falcon]

Thanks for your reply firstly
I also agree to the fact that it was explained very well, the whole system of SAR
I meant to ask the guidance regarding the actual working operation of the comparator alone in terms of its each sections' part(diff. amplifier, SR latch and flipflop) in the working of the comparator.i am getting kinda confused with it and thats why i thought of asking some suggestions
Otherwise I am quite clear about the SAR operation in general as its quite well described in the paper like you said
thanks

falcon

 

[erikl]

... I meant to ask the guidance regarding the actual working operation of the comparator alone in terms of its each sections' part(diff. amplifier, SR latch and flipflop) in the working of the comparator. i am getting kinda confused with it ...

there are three phases in one cycle.

When CLK1 is high, comparator is in the reset mode, which forces node a and b to be equal.

Next, when both CLK1 and CLK2 are low, M3 and M4 start to regenerate.

When CLK1 is low and CLK2 is high, transistors M3, M4, M7, M8 form two back to back inverters that cause voltage at node a and b to grow exponentially in the opposite directions.

The S-R latch part is used to store the output after the third phase and remains in this state in the next reset mode.

The nodes a & b are the common drain nodes of M5,M7,M9 & M6,M8,M10, respectively.

Now tell us, which part are you confused with?

 

[the_falcon]

Hi Erik, Thanks a lot for your reply again
Regarding its operation,I actually got confused where the nodes a and b are in the diagram.But now I am OK as u explained that one.
A switch can either be implemented by a single NMOS or a NMOS-PMOS-Parallel combination as far as I know
In that way, the clk1 switch is implemented by a single NMOS M11 in the figure
But what about clk2.? M5 and M6 are again single NMOSs and so its no doubt there
but what about those PMOSs connected at the top row of the flipflop section in the figure(M9 and M10, the outermost PMOSs in the top row of the FlipFlop section)
What are they supposed to do.I am getting confused in this part and so it would be great if you explain in this part of the comparator.
Thanks again Erik

Falcon

 

[erikl]

During the phase when both clk1 & clk2 are low, M9 & M10 -- which then are activated -- just hold the current status of the FF in order to enable the undisturbed transfer of the current (i.e. not any more changeable) state to the S-R latch.

 

[the_falcon]

thanks again
so am i right that both the NMOSs M5 and M6 just the switches set to realize for clk2
also could you tell me as why the current source is connected to the M4 side of the flip flop section of the diagram

 

[erikl]

so am i right that both the NMOSs M5 and M6 just the switches set to realize for clk2

Yes, I think so.

... why the current source is connected to the M4 side of the flip flop section of the diagram

M12 sources twice the current of M1 or M2. So I think its purpose is the initialization of the M3...M6 FF to its quiescent state, e.g. to a "0" start state. A connection to M3 then would initiate the "1" start state.

 

[the_falcon]

hi erik,
thanks for giving me valuable suggestions regarding the circuit I asked the explanation for. I have another doubt. Is there any way for me to get some gain from the differential input stage M1 and M2 though I dont have any load connected to it.

I am getting confused with this factor as a comparator, the differential amplifier is supposed to have some gain to reduce the offset voltage of the comparator. I will attach the relevant technical paper with this message

thanks a lot for your suggestions.it really is a big help for me

falcon

 

[erikl]

Is there any way for me to get some gain from the differential input stage M1 and M2 though I dont have any load connected to it.

I am getting confused with this factor as a comparator, the differential amplifier is supposed to have some gain to reduce the offset voltage of the comparator. I will attach the relevant technical paper with this message

Of course M1 and M2 have a load connected to them: In the paper these loads are depicted as Ca resp. Cb "With these dimensions the total capacitance at node a or b is about 0.05 pF". At the beginning of the regeneration phase (t2), "the amplification gain will be 54 within 1 ns" (p. 210, 3rd paragraph at the right).

 

[the_falcon]

thanks..i thought the same too..but i dont get any gain at all if i connect the circuit in that configuration with all the mentioned dimensions and also with the same bias current they mentioned. could you have any clue as why i am not able to get it. by the way, i am using 65 nm technology

 

[erikl]

i dont get any gain at all if i connect the circuit in that configuration with all the mentioned dimensions and also with the same bias current they mentioned. could you have any clue as why i am not able to get it. by the way, i am using 65 nm technology

The comparator in the mentioned paper was fabricated in 1500 nm technology -- a factor of 20 larger than your tech. Did you also use min. sized structures, as (W/L)12 = 65nm/65nm (if this is the allowed min. size) ? If not, the MOSFET's intrinsic caps will be much larger than the parasitic ones (αW4 » Cp), which won't result in a min. τreg and good gain.

I'd also suggest to use a lower current IB, at least by a factor of 4 , something between 1 and 5µA .