Explain me the latchup for PNP transistor

[cooldude040]

Latchup

When PNP transistor will be on?? I think if the Vbe<0.7 then it will be on am i right? So can anyone explain this statement?

atchup may begin when Vout drops below GND due to a noise spike or an improper circuit hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn on Q2 (I Rsub > 0.7 V ), this will draw current through Rwell. If the voltage drop across Rwell is high enough, Q1 will also turn on, and a self-sustaining low resistance path between the power rails is formed. If the gains are such that b1 x b2 > 1, latchup may occur. Once latchup has begun, the only way to stop it is to reduce the current below a critical level, usually by removing power from the circuit.


The link for this material is

http://www.piclist.com/images/edu/drexel/ece/www/http/ECE/ECE-E431/latch-up/latch-up.html


Please explain this..Its very important....This point is something related to Ground Bounce and Power bounce so Can anyone explain for PNP transistor?? How this is getting on? As it is a pnp transistor so to make this transistor on we need Vbe<0.7 am i right????? check out and explain me as soon as possible...........


I will be grateful to u if u can do this for me

Bye take care

 

[A.Anand Srinivasan]

Latchup

i see a little contradiction and diagram in the explanation given in the link that you've provided... because once Vout goes to -0.7V or above and when the author says the transistor Q2 is forward biased... it just means that the n+ connected to the Vout pin must be the one which would be acting as Q2's emitter not the n+ connected to the Ground pin... because if it were as per the second diagram (i.e. the circuit diagram) then Q2 would be needing 0.7V or above to turn on not -0.7V or above...

 

[FvM]

Re: Latchup

I agree, that the explanation isn't exact, particularly this sentence Vout is the base of the lateral NPN Q2. To my opinion, Vout is a second emitter of Q2, while the substrat is the base. Anyway, forward biasing of substrat junction diodes causes current flow in the substrate, that can trigger latch-up in a susceptible (bad designed) IC. The n-well junctions behave similar, so the latch-up can also be started by exceeding VDD at a p-FET source or drain.

A detailed discussion can be found in many CMOS textbooks, e. g. Razavi, Design of Analog CMOS Integrated Circuits.