Guys, I have two questions in mind when talking about setup and hold times.
The first is about violations - Suppose we have some setup time, say 7ns and we have 1ns setup violation. Does it mean that data arrives 6 ns before the clock edge or it means that data arrives 1ns after the edge?
And the second concerns hold times - what assures that my design has the required hold time. My opinion is that delays of an output signal of a stage with respect to the clock assure the hold time of the next one, for the next clock edge. Is this correct?