exam quetion please help

[rafia123]

Describe, using VHDL, a 4-bit parallel load shift register. The register is to have a synchronous load signal (L) and an asynchronous reset (CLR) and will function synchronously using a clock (CLK) signal. The system has a serial input (SIN) a 4-bit parallel input bus ( D[3:0] ) and a serial output (SOUT).

 

[yura717]

**broken link removed**
https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/4-Bit_Shift_Register


https://www.cs.uregina.ca/Links/class-info/301/register/lecture.html

 

[rafia123]

**broken link removed**
https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/4-Bit_Shift_Register


https://www.cs.uregina.ca/Links/class-info/301/register/lecture.html

which one is the right one ? i am confused as i dn't know VHDL at all

 

[yura717]

if you dont know VHDL ... do you know digital electronics /schematics/ ?