event construct in verilog BFM

[asicengineer1]

Hi,
can somebody tell me how the event construct (-> ) is used in writing BFM in verilog? When does a BFM start to initate transcations to the DUT? i know that some event is generated at the start and based on this, the txns are started, but, haven't come across a verilog code like that. It'll be nice if somebody can provide some examples.

 

[mkrishnap]

Hi asicengineer1,

The “event” construct is simple in verilog. Only two operators are used, “->” for triggering and “@” for waiting the event to trigger. Both of the operators can be used in any of the initial or always blocks.

See the following counter example, where an always block will increase the count by 1 for each posedge of the clk. For every value of count divisible by 5, the event "dev_by_5" is made to trigger in that block. The other always block and initial block will use this even to print the count.

reg       clk;
reg [4:0] cnt = 5'b00000;
event     dev_by_5;

always @ (posedge clk)
begin
 cnt = cnt + 1;
 if(cnt % 5 == 0) 
   begin
     ->dev_by_5;
   end
end

  
always  @ (dev_by_5) begin
  $display("cnt @ always block = %0d", cnt);
end

initial
begin
 @ (dev_by_5)
 $display("cnt @ initial block = %0d", cnt);
end

The output will be

cnt @ always block = 5
cnt @ initial block = 5
cnt @ always block = 10
cnt @ always block = 15
And so on….

-mkrishnap