theHermes
Newbie level 6

I need to design a clock divider as part of my verilog program for SPI but unfortunately I have a few errors and I am not able to correct the errors.
the code is as follows:
module clockdivider(mclk,rst,sclk);
input mclk;
input rst;
output sclk;
reg [7:0]divide;
integer i;
always@(negedge mclk)
begin
if (rst==1)
begin
sclk=0;
i=0;
end
else
begin
assign sclk =mclk/(divide+1)*2
i=i+1;
end
end
endmodule
please evaluate the errors-
thanks.
the code is as follows:
module clockdivider(mclk,rst,sclk);
input mclk;
input rst;
output sclk;
reg [7:0]divide;
integer i;
always@(negedge mclk)
begin
if (rst==1)
begin
sclk=0;
i=0;
end
else
begin
assign sclk =mclk/(divide+1)*2
i=i+1;
end
end
endmodule
please evaluate the errors-
thanks.