ogulcan123
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You followed the designguide in datasheet chapter 3.8.1.1?
Please provide an extract of the Ethernet PHY circuit, showing the LED1/REGOFF pin and the connected parts.
Because the LED pins have different function in different pinstrap defined configurations, you should show the complete schematic.
A likely fault, particularly with prototypes is to have missing solder joints of the small chip scale package.
You can get much information about the PHY state through management interface by dumping all registers.
I believe there are at least two schematic errors:
- LED2 must be equipped with an external pull-down resistor to select the right REFCLK mode and active high LED2 level
- VDDCR is the internal 1.2V regulator node and must never be connected to 3.3V. Supplying more than 1.5V will damage the chip. VDDCR will be connected to external bypass capacitors only in the selected internal regulator mode.
See below a working STM32 interface
View attachment 131389
I would also suggest to add a weak pulldown to LED1 pin, to get sure Int. LDO is activated always.
You might also consider to add additional pullups on MODE0-2 pins (depends on the pin capacitance of the STM32 & traces)
VDDCR pin needs some ext. buffer caps connected to stabilize (1µ||470p, see chater 3.9.2), you -if still connected- have 2x 1n...
Reckeck your oscillator circuit, looks somehow strange with the series resistors and the additional C to GND. Maybe it's not starting to oscillate. The design FvM posted looks more common ;-)
With pulldown on LED2 pin, you should see 50MHz clock on pin14 (I hope the STM32 connected is an input to the signal). If not, you have an oscillator problem....
It's essential to have a certain amount of bypass capacitance for each node. In case of the 3.3V supply, there will be probably more capacitors at other point of your circuit, having e.g. 100 nF at each supply pin should be sufficient then. Proper operation of the internal 1.2V supply depends on sufficient VDDCR bypass capacitance.
Regarding 1 Mohm resistance, I found that it's not populated in the reference design, so it's apparently not required. But apparently doesn't hurt because I have in in a number of designs.
Yes the Caps on VDDCR are mandatory, its the supply for the core logic :!:
You already mentioned the ripple you observed, which is 120mV and at spec limits (1.14V .. 1.26V)...
The 1Meg is not that critical. Needed to support start of oscillation, but depends on the crystal you use.
Please show us your current schematic, as it seems there are diffences to the one you posted.
Have you checked pin14 for 50MHz? It will give us a hint where to focus on.
Good so far. Question is if the 25 MHz oscillator and refclock output are working as well.
Consider that probing the crystal oscillator nodes with a passive oscilloscope probe might stop oscillations. Most likely at oscin, possibly at oscout node too. If you don't have a high impedance active probe, a 1k - 10k series resistor for the probe might help to see the oscillations. Refout can be probed without problems.
Yes, that's also my observation. LAN8720 crystal is even oscillating with reset input hold low.see that the ethernet chip's crystal has an oscillation without any signal from the MCU
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