estimation of gate count

[sp3]

report_area gate count

Hi all...

Can anyone of you tell me the command/option to estimate the number gates in a design using Astro and DC.. I am able to get only number of stanadard cells..

Thanks in Advance,
sp3

 

[bulx]

Guess 2 ways possible:
1. look up library and get area of each type of cell, divide by area of 2 input and gate to get equivalent gatecount of each type of cell. Find number of each type of cell in design and calculate count. Prob need a perl script to do this.
2. Some technologies given an approx gate count per mm^2 number. If you know physical logic area you can use this figure to arrive at gate count.

Both need library info.
-b

 

[gliss]

The library should report the gate count of each standard cell where 1 gate is a 2 input NAND gate with a 1x drive strength.
So a 3 input NAND gate with 1x drive will be 1.5 "gates", a 4 input, 2 "gates", a buffer 1 "gate", an inverter .5 "gates", a D flip-flop is 6.5 "gates"
Why is the gate count number much more important that the number of standard cell instances and total area?

 

[shield]

And are there anybody explain how to caculate the count for FPGA and ASIC of the same count?

 

[gliss]

I think you mean the gate count for the FPGA and ASIC implementation of the same design? For that you should look at the synthesis reports for the FPGA and the FPGA vendor's library documentation. The synthesis reports will tell you how many resources the design uses and the FPGA library documentation will tell you how FPGA resources are translated into gate counts.

 

[sp3]

Hi all,

I raised my doubt just because when people talk about ASIC/processor chip, then they talk it interms of "Multi millon Gates" only. So I was wondering , why only "Multi millon Gates" but why not "Multi million Standard Cells" and if ""Multi millon Gates" how do we estimate the count??

thanks,
sp3

 

[gliss]

This topic is a little tricky. This falls under the category of what is design metrics. Like "how big is the chip?", "how fast is the chip?", "how much power does it consume?", etc. Sometimes people confuse design metrics on purpose in order to achieve their goals. So someone might say "transistor count" instead of "gate count" when describing the design if they want a bigger number.
As a designer, none of this should really matter to you much. I find that marketing and consumers tend to put more emphasis on these numbers.
As a designer, what I'm concerned about is how big the design is interms of slilicon aera (mm x mm) and how man standard cell parts, and which TYPE of standard cell parts my design uses.
So if someone asked me how big my design is, I'm usually talking to another engineer at my company or on my project. Then I tell them the estimate of the standard cell library instances.
If someone OUTSIDE the company asked me how big my design is. I tell them a very rough estimate of GATE counts, i.e. how many 2-input, 1x drive strength NAND gates the design might be equivalent to. So my disign might use 400k standard cell instances of all types and parts. Maybe even some special cells in the library that would have complex function. Then there are macros, memories and custom cells,etc. So the standard library parts may not be an accurate description of how the big or small the design is to an outsider because the design might be closer to 1.2 millin 2 input NAND gates.
It all depends on who your audience is and what type of information you are trying to communicate when you use terms like "standard cell library instance count" vs "raw gate count".
HTH

 

[Clunixchit]

Hi all...

Can anyone of you tell me the command/option to estimate the number gates in a design using Astro and DC.. I am able to get only number of stanadard cells..

Thanks in Advance,
sp3

1. Count the number of (hier) instances on the design
2. Multiply that number in accordance to their respective gate count (see its attributes)

 

[shankarmit]

U can get total standard cell are using DC report_area command. Then u take area of a nand gate, and divide it to get approx gate count.

Thanks

Regards
Shankar

 

[FLEXcertifydll]

Normally, you can find the area of a cell in the library, of course, you can find the same value in datasheet from library vendor.
from DC you will get the area about the design, and from lib or DS get the one gate area, so you will get the gate count.

 

[MarcS]

Gliss has given the correct answer.

 

[p_shinde]

in short and simple get area of a 2 input nand gate and multiply it with no. of standard cells thats ur gate count